1. Field of Invention
The present invention relates to the customization of electronic devices using radiant energy to configure interconnect structures, and more particularly to a compact arrangement of these structures and active circuitry on an integrated circuit.
2. Related Art
Custom or application-specific integrated circuits (ASICs) are frequently used to implement new circuit designs. The fabrication processes for an integrated circuit (IC) includes the following basic steps:
1) form a layer of conductive or insulative material on the upper surface of a silicon or semiconductor wafer;
2) coat the conductive or insulative layer with a photoresist (positive or negative), which is then cured and dried;
3) expose the photoresist (resist) to an intense light source through a precision mask to define specific patterns on the resist;
4) develop the resist to remove portions not selected by irradiation through the mask (exposed portions if a positive resist is used, unexposed portions if a negative resist is used);
5) etch away the portions of the conductive or insulative layer exposed by the removed portions of the resist;
6) remove the remaining resist;
7) repeat steps 1-6 for each layer formed on the IC.
One consequence of this fabrication process is that several precision custom masks may be required for each IC. Because precision custom masks are costly to manufacture, a large quantity of each IC must be produced in order for the fabrication process to be economical. However, as technology advances, circuit designs become more application-specific and are typically required at a much lower volume than the more generic ICs, thus making fabrication of such application-specific ICs more expensive. This need for lower cost-per-unit ASICs and other needs of the ASIC manufacturer and user are not being met with the conventional fabrication process.
The objectives of the ASIC user and manufacturer can be categorized into four primary areas. One objective is to feasibly manufacture a small number of prototype units (i.e., one or two units). This keeps the design costs low because only the required number of test units are manufactured, thereby saving costs for the unused and unneeded units. A second objective is to minimize the costs of each iterated test unit because a single application may require numerous prototype units for testing and modification. A third objective for the ASIC user is to reduce the lead-time to produce both prototype and production units so that the design can be developed and placed into production as soon as possible, thereby shortening the time-to-market schedule for the final circuit design. A fourth objective is to minimize costs for both prototype and production units, regardless of the number manufactured.
In an attempt to meet these objective, a current practice is to use gate arrays to customize integrated circuits. Gate arrays are mass-produced integrated circuits containing generic arrays of circuit elements ("gate array blanks"), which can be customized into application-specific ICs with a small number of masks defining custom interconnections of the circuit elements at the final steps of fabrication. The gate array blanks can be manufactured up to the customization steps and stored away until an order for a particular application-specific circuit is received.
Typically, in a two-layer metal technology, customizing the gate array blank requires processing three layers: a first metal layer, an insulation layer, and a second metal layer, in that order. The basic steps are as follows:
1) deposit the first metal layer on a contact layer, which connects the first metal layer to the circuit elements below;
2) coat the first metal layer with resist, which is then cured and dried;
3) expose the resist through an application-specific mask;
4) develop the resist to remove the unwanted portions of the resist, i.e., the desired electrical connection portions;
5) etch the uncovered portions of the first metal layer;
6) remove the remaining resist;
7) deposit the insulation layer on the first metal layer;
8) coat the insulation layer with resist, which is then cured and dried;
9) expose the resist through a second custom mask;
10) develop the resist and remove the unwanted portions;
11) etch the uncovered portions of the insulation layer to form openings ("vias") in the insulation layer for connecting the first and second metal layers;
12) remove the remaining resist;
13) deposit the second metal layer on the insulation layer, allowing the deposited metal to fill the vias;
14) coat the second metal layer with resist, which is then cured and dried;
15) expose the resist through a third custom mask;
16) develop the resist to remove the unwanted portions;
17) etch the uncovered portions of the second metal layer;
18) remove the remaining resist;
19) deposit a passivation layer on the second metal layer; and
20) configure the passivation layer using a general purpose mask to provide connections for the ASIC thus formed.
Therefore, gate array processing reduces cost and lead-time to manufacture ASICs. However, even though gate array processing meets portions of the third and fourth objectives, the other objectives are not met due to the high costs of precision configuration masks. Furthermore, the need for precision configuration masks limits the extent that costs and lead-time can be reduced.
An alternative method is to use direct-write on wafer technology on gate array processing to replace the steps which require custom configuration masks. However, using programmable direct-write machines can still incur substantial costs to the manufacture of prototype and production ASICS. Electron beam (E-beam) direct-write technology employs high-cost equipment with a low throughput. On the other hand, laser-based direct-write systems do not have the resolution needed to meet the performance and total die size requirements of present designs. Even though less expensive than E-beam systems, laser-based systems are still more expensive and of lower precision than standard optical reduction steppers or other comparable methods using a standard set of precision photomasks.
Another alternative method for IC customization is to use arrays of radiant energy or laser-configurable fuses. In such methods, an array of laser fuses connects various inter-layer and intra-layer circuit elements. A radiant energy beam or laser then "blows" selected fuses to sever the electrical connection for circuit customization. Because the laser beam is applied directly to the fuses, the area above the fuses are commonly left open. It is also common for the area around and beneath the fuses to be free of active circuitry, i.e. transistors, resistors, signal lines, and junctions, to prevent the circuitry from being damaged from the heat of the radiant energy pulse. As a result, when compared with other conventional methods, the overall area of the integrated circuit increases and device density decreases since active circuitry cannot be placed underneath or near these fuses.
Device density is further limited when using conventional fuses because of minimum fuse length requirements. Since laser energy requirements are high, the fuse length in a fuse-programmable device is governed by the need to isolate the heat from the laser from the interconnect lines in contact with the fuse. If the fuse is too short, the heat may be transferred along the length of the fuse to the interconnect lines, resulting in possible damage to the lines.
Accordingly, it is desirable to customize integrated circuits without the drawbacks discussed above associated with conventional methods.